Averatek Catalytic Precursor Ink

This ink controls the horizontal dimensions of line width and spacing.  The vertical dimension of metal thickness is controlled by using a proven additive plating process that deposits metal only on the patterns defined by the precursor ink.  Interior of vias can be plated with metal using the same process and at the same time that the surface conductors are coated.  The precursor ink promotes good bonding between the thin metal patterns and the substrate, eliminating the need for adhesives and other tie-coat bonding methods.


Averatek technology can create metal lines/spacing widths below 5 microns and deposit copper to a thickness level from 0.1 micron up to 10 microns or more. The additive feature of this technology allows the direct deposition of copper on a substrate in the pattern specified by the circuit design artwork without tie coat, adhesive, etching, or waste of copper.

Additional Technology information links:

• Averatek’s Process

• High Conductivity Metal

• Averatek’s Ink

• Fine Line and Spaces

• Thin Copper

• Metalizing Via Surfaces

• Semi-Additive Process Variation

• Design Guidelines

Averatek Additive Process

Averatek’s process consists of 6 basis steps.

1. Drill vias in the substrate using either mechanical or laser drills. (Note: This step is optional if the customer’s process includes creating vias after the Averatek process has been completed or does not include vias. Prepare the substrate material for processing. In most cases this is a simple cleaning and mounting of the material in the appropriate material handling system.

2. Coat and cure the substrate with the special Averatek Atomic Layer Deposition (ALD) precursor catalytic ink, resulting in a subnano-layer (<1nm thick) of catalytic material.

3. Image the subnano-layer using photolithographic techniques to create the patterns where copper will be deposited. The geometry of lines and spaces that can be produced at this point is anything above 3 µm.

4. Deposit electroless copper on the designated patterns. The copper thickness ranges from 0.1 µm to 1.0 µm.

5. If thicker copper is needed, then the sixth step is electrolytic copper plating.

High Conductivity Metal

Unlike conductive inks which tend to be highly resistive composites of metal flakes, polymers, and other fillers, the copper  deposited on the Averatek imaged patterns takes the form of fine grain, densely packed, ductile, smooth, annealed, and highly conductive material which has electrical properties similar to that of high quality copper wire or rolled copper foil.

Since many of the applications requiring fine line geometries have to support high speed and therefore high frequency signals, the smoothness and quality of the conducting metal is critical.  The process developed by Averatek produces conductor whose cross sections are rounded and whose surfaces are smooth.  Both qualities are ideal for high frequency circuitry to minimize cross talk, shorts, and energy losses.

Fine Lines & Spaces

The two dimensions of length and width of metallized patterns are created with the Averatek imaging technology.  Averatek can deliver fine lines down to 5 µm in width and spacing on the same substrate with geometric features that can be measured in hundreds of µm.  A sample of copper lines created on commercially available polyimide is shown in Figure 5.

Thin Copper

The third dimension of height or thickness of the metallized patterns is created using conventional but finely tuned electroless and/or electrolytic plating processes. By using this additive plating approach, the thickness of the copper in the metallized patterns can be custom selected.

The typical conventional processes in the rigid and flex circuit board industries today start with sheets of copper foils (available in limited thicknesses) that are laminated to a substrate. If the required thickness is different than the foil thicknesses available, then the copper has to be etched down or plated up to the necessary thickness. The trend of higher density and finer line circuits is accompanied by a trend to thinner copper.

An alternative to the laminated copper foil substrates that has been used for many years is sputtered or vacuum deposited copper. This type of process often requires that a thin tie coat of chromium, nickel, or tungsten be vacuum deposited on the substrate before the copper is vacuum deposited. These processes have provided a non-adhesive approach to achieve thin metal, but the additional expense of the vacuum sputtered processes and the compatibility issues of the tie coat layer create limitations for applications. The Averatek additive process is also non-adhesive, but is more application friendly with both additive and semi-additive manufacturing potentials, and provides excellent mechanical properties.

Metalizing Via Surfaces

Metalizing via surfaces at the very earliest stages of a production process is an innovation that offers the elimination of several process steps that are currently embedded in the conventional manufacturing of flexible circuit boards that use subtractive and semi-additive processes. Typically vias are plated and filled at later stages in the flex circuit board layer manufacturing process because of the manufacturing processes associated with flex circuit materials that are either adhesive-based or vacuum sputtering on metal tie coats. Using the precursor ink technology described above, copper can be deposited on the inner surfaces of vias at the very earliest stages of a flex circuit production process.

The demonstration of using the print and plate method for vias is shown below. The first image is a microscopic picture of a via that is 35 microns in diameter and was laser drilled in commercially available polyimide film, it is 25 microns thick.

A Semi-Additive Process Variation

Despite the many advantages of using a fully additive metallization process for making printed circuits, there are some circuits where design and copper thickness requirements make a fully additive approach difficult.

Typically a semi-additive approach involves the creation of a large area pattern (possibly the entire surface) of copper, which then produces a micro-layer of copper ( < 0.3 µm). This thin copper layer then can act as a ground plane for Averatek’s electrolytic process. This approach requires a photolithographic step to image the pattern of copper to be built up on the ground plane and a flash etch step to remove the seed layer of copper not patterned after the electrolytic process is completed. All of the benefits for fine line geometry from the additive process are preserved as well as the cost savings by avoiding the need for sputtered vacuum deposition. However, there is some additional post plating processing required when compared to the fully additive process.